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IBM 5161 - SOME COMMENTS ON THE CIRCUITRY OF THE EXTENDER CARD
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Enable/disable of extender card
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The primary flip-flop (pins 1 though 6) in U13, determines whether the extender card is enabled or disabled.
- If flip-flop set, the extender card is enabled.
- If flip-flop reset, the extender card is disabled.

The flip-flop is set at application of power (via pin 4), thus enabling the extender card.

U1 appears to be ensuring that, if the flip-flop is already set (extender card enabled), that the flip-flop remains set when a 'read status' of the card is done.

When the flip-flop is set (extender card enabled), the /Q output (pin 6) is low, and does the following:
- That low going to pin 3 of U21, effectively enables the wait-state generation circuiry  [see 'Wait-state generation circuiry' below]
- That low going to U8 (a 74LS244), enables /MEMW and /IOR passing through U8 via pins 8,6,12,14


Wait-state generation circuiry
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Gate #1 in U14 is the main gate. A low output (with certain other requirements down the track) results in a wait state being generated.
Gate #1 has two inputs, from U6 and U21:

U6 detects any read/write of segment F (A19=1, A18=1, A17=1, A16=1).  On detection, its low output disables wait-state generation.


Re U21, the 74LS85 address comparator.
IBM have configured pins 2/3/4 in such a way that, when the card is enabled (input pin 3 will be low), output pin 5 will be: 

CONDITION                                                     PIN 5

1. Card enabled, and ISA address less than DIP address        Low
2. Card enabled, and ISA address same as DIP address          High   (per 74LS85 truth table, pin 5 always high if address match AND 74LS85 pins 2/3/4 are all low)
3. Card enabled, and ISA address greater than DIP address     High

The low in condition 1 above will disable wait state generation.

As for the high in conditions 2 and 3, whether or not a wait state will be generated will depend on whether or not another condition is met.
Looking at the card circuitry, that other condition is: A memory read/write operation that is not part of RAM refresh.